1. Field of the Invention
This invention relates to a semiconductor device with a guard-ring structure for achieving a high breakdown voltage property and a method of fabricating the device. More specifically, the invention relates to a semiconductor device, in which upper and lower electrodes of a planer-type device chip are bonded to upper and lower conductive frames respectively with solder material.
2. Description of Related Art
In the field of power-use semiconductor devices, there has been provided such a technique that guard-ring layers are formed to surround a terminal diffusion layer, and a field plate is disposed above the guard-ring layers for controlling the depletion layer extended in a high-resistive semiconductor layer to achieve a high breakdown voltage (see, Unexamined Japanese Patent Application Publication No. 2003-101039).
FIG. 11 shows a sectional view of a main portion of a planer-type semiconductor device with a guard-ring structure, to which a wire bonding scheme is adapted. This semiconductor device chip is a diode, which has a high-resistive N-type semiconductor substrate 101 serving as a base semiconductor layer; a P-type diffusion layer serving as an anode layer 102, which is selectively formed in the top surface of the substrate 101; and an N+-type cathode layer 103 formed in the bottom surface.
In the top surface of the N-type base layer 101, a plurality of guard-ring layers 104 are formed of P-type diffusion layers as to surround the anode layer 102. Formed in periphery of the chip surface is N+-type channel stopper layer 105.
The top surface of the device is covered with an insulating film 106 such as silicon dioxide, and an anode electrode 107 is formed to be contacted with the anode layer 102 via a contact hole formed in the insulating film 106. A part of the anode electrode 107 is extended on the insulating film 106 to serve as a field plate 107a overlying the first guard-ring layer 104. A main field plate 108 overlying the second and third guard-ring layers 104 and an equi-potential ring (EQPR) electrode 109, which is connected to the channel stopper layer 105 and extended on the insulating film 106, are formed simultaneously with the anode electrode 107.
A passivation film 110 is formed on the top surface in which the anode electrode 107, field plate 108 and EQPR electrode 109 are formed. The passivation film 110 is a plasma CVD film (for example, silicon nitride or silicon dioxide) or a polyimide film. A hole is formed in this passivation film 110, and then wire 112 is bonded to the anode electrode 107.
The above-described high-voltage semiconductor device with the conventional wire-bonding scheme has drawbacks such as: it is difficult to thin the device due to the bonding wire; and it is difficult to secure a high current-proof. To solve these problems, it is desirable to use a solder-bonding scheme such as to bond a semiconductor device chip to conductive frames with solder material.
However, when such the solder-bonding scheme is adapted to a planer-type semiconductor device, another problem occurs. For example, FIG. 12 shows an example, in which the anode electrode 107 of the same semiconductor device chip as shown in FIG. 11 is bonded to a conductive frame 113 with solder material 111. For achieving such the solder-bonding, it is required to use a laminated metal film (for example, V/Ni/Au film), which has a good wetting property for solder material, for the terminal electrodes (i.e., anode electrode and others) in place of a normally-used Al electrode.
In case such the laminated metal film is used, however, it is not permitted to use the passivation film 110 as shown in FIG. 11. The reason is as follows. If the passivation process is performed in a high temperature circumstance of about 300° C. or more after having formed the anode electrode, it will be generated melting of Ni, oxidization of Au and the like, and thereby resulting in that the solder-wetting property of the anode electrode is deteriorated.
Therefore, FIG. 12 shows such an example in which anode electrode 107 is solder-boded to frame 113 without a passivation film covering the anode electrode 107 and field plate 108. In this case, however, sprayed solder material 111a may be stuck between anode electrode 107 and field plate 108 to short-circuit therebetween. As a result, the mode of the depletion layer extending at a reverse bias application time may become different from a desirable state, and the breakdown voltage property will be deteriorated.
Additionally, in the structure of FIG. 12, when a high voltage is applied to the device, it is easy to occur space discharge (i.e., spark) between the field plate 108 and EQPR electrode 109 because there is no passivation film. This will lead to insulation breakdown and deterioration of the device characteristics.
As described above, there are various problems in the double-sided solder-bonding scheme for planar-type semiconductor devices. Therefore, currently used double-sided solder-bonding high-voltage semiconductor devices are not formed as planer-type ones, but usually formed as mesa-type ones. However, mesa-type semiconductor devices have some astatic factors as follows: leakage current at a reverse bias time is larger than that of planer-type one because the PN junction is terminated to the mesa slope; and thermal runaway may be easily arisen under a high temperature circumstance.